MiniMax H3 on Dual DGX Spark: Recipe and Numbers
MiniMax H3 is a joint video + stereo-audio DiT, not a chat model. On this fleet the production video path is two independent DGX Spark ComfyUI workers. DeepSeek V4 Flash stays down while they run. M3 Ultra is rollback, not the factory.
Matched FL2VA baseline (960×544 · 107 frames · 28 steps · seed 47) finished concurrently in 526.7 s and 506.8 s. Dual-lane wall was 527 s — almost two full clips in one Spark-length run.
Topology
Mode A: exclusive video factory. Do not read this as “H3 plus the agent brain on the same pair.”
What we pin
| Piece | Pin |
|---|---|
| Image | milo/minimax-h3-comfyui:2026-08-06 |
| ComfyUI | 0.30.0 @ 2eb609766a749e3104485979615e062e401bab97 |
| Torch | 2.9.1+cu130 / torchvision 0.24.1 / torchaudio 2.9.1 |
| Kernels | comfy-kitchen 0.2.26 |
| DiT | pruned INT8 ConvRot FL2VA · sha256 e889202c…c47a |
| Text encoder | stock Qwen3-VL 32B NVFP4 AWQ · sha256 35a88d51…f2c6 |
| VAEs | video FP16 · audio FP32 |
| Weights rev | eb8a16107c595128b3a578f82d2ce2f75920c355 |
| Listen | container 0.0.0.0:8188, publish 127.0.0.1:8188 only |
| Flags | --use-pytorch-cross-attention --disable-pinned-memory --reserve-vram 4 --cache-none --disable-all-custom-nodes --preview-method none |
| Cold-start gate | h3ctl refuses start unless ~90+ GiB MemAvailable |
No SageAttention, EasyCache, Turbo LoRA, Spectrum, Heretic TE, or 2K upscale in this baseline. Those are optional overlays and change quality, not just wall time.
Recipe
One worker per Spark. Same compose, same checksums, same image tag. DeepSeek V4 Flash is stopped first so UMA is free.
# on each Spark, from the H3 service root
# 1. DS4 must be down for Mode A
# 2. verify weights
./h3ctl verify-models
# 3. build once (CUDA 13 / PyTorch 2.9.1 arm64)
./h3ctl build
# 4. 90 GiB free + loopback :8188 clear, then start
./h3ctl start
./h3ctl verify
Matched job used by the numbers below:
python3 run_job.py \
--name modeA-perf \
--first data/input/baseline-first.png \
--last data/input/baseline-last.png \
--prompt data/input/baseline-prompt.txt \
--width 960 --height 544 --frames 107 --steps 28 --seed 47 \
--timeout 3600
Submit both Sparks at once. Hold the dispatcher lock only until each Comfy /queue shows the job. Holding it for the whole generation serializes the factory.
Measured — August 12, 2026
Concurrent FL2VA, identical pins and seed, DS4 down, baseline compose (no --lowvram).
| Lane | Wall | vs Aug 6 Spark 1 (524.8 s) | vs Aug 6 M3 Ultra (713.0 s) | Min free RAM |
|---|---|---|---|---|
| Spark 1 | 526.719 s | +0.4% | 1.35× faster | 68.67 GiB |
| Spark 2 | 506.787 s | −3.4% | 1.41× faster | 69.54 GiB |
| Dual aggregate | Value |
|---|---|
| Both done (wall) | 526.7 s |
| If run serially | 1033.5 s |
| Parallel efficiency | 1.97 / 2.00 |
| Output | H.264 + AAC 32 kHz stereo · 4.458 s · 960×544 · status succeeded |
Spark 2 was a bit faster this run. Spark 1 is within noise of the August 6 solo anchor. Two lanes are almost fully concurrent: ~9 minutes of wall for two matched clips instead of ~17 minutes serial.
August 6 anchors (same canvas / frames / steps) came from the earlier dual-Spark commissioning: Spark 1 solo 524.760 s, M3 Ultra MLX 712.974 s. Today’s rows are new receipts from this session.
Three exclusive modes
| Mode | Use | Stack | Status |
|---|---|---|---|
| A. Video factory | MHR / product B-roll | Dual solo H3, DS4 down | Production default — this post |
| B. Agent brain | Day-to-day Hermes | DS4 1M @ 0.85, H3 down | Production agents |
| C. Co-tenancy | Light video while agents stay up | DS4 200k @ 0.76 + H3 --lowvram --reserve-vram 48 | Canary only (August 11) |
Mode C can finish tiny concurrent FL2VA (~50–52 s/lane at 608×352 / 22f / 4 steps) with DS4 still answering. It is not the MHR quality profile. Do not treat a 4-step smoke as a 28-step factory result.
Verdict
For hardware-review B-roll, keep Mode A: pinned Comfy 0.30, pruned INT8 FL2VA, stock NVFP4 TE, one worker per Spark, DS4 off. The factory is back on the August 6 pace — about 8.5–8.8 minutes per matched 107-frame clip, two at a time.
M3 Ultra stays the Apple-native comparison path (MLX H3 post). Next speed work, if any, is a one-Spark Sol/FBC overlay A/B against this exact 960×544 / 107f / 28-step receipt — not a silent stack swap.